MOS transistors formed in a well region are used mainly in integrated semiconductor circuits having both N-channel MOS transistors and P-channel MOS transistors. Due to the fact that the substrate or epitaxial layer, respectively, usually is of a uniform conductivity type, it is not possible to form therein both the drain and source regions of an N-channel MOS transistor and the source and drain regions of a P-channel MOS transistor. This is why the substrate or epitaxial layer of a first conductivity type is formed with a well region of opposite conductivity type, in which one of the two MOS transistor types is formed, whereas the other MOS transistor type is formed in the substrate or epitaxial layer, respectively.
There are also integrated semiconductor circuits having, in a substrate or an epitaxial layer of very low conductivity of a specific conductivity type, both a well region of the same conductivity type and a well region of the opposite conductivity type. One well region serves to receive the one MOS transistor type, and the other well serves to receive the opposite MOS transistor type. The two well regions are so to speak isolated by the region of the substrate or epitaxial layer, respectively, of very low conductivity that is located therebetween.
For reasons of simplicity, the following description speaks only of a substrate, with this term at all times comprising the possibility that this may also be an epitaxial layer.
An example that frequently occurs in practical application is a CMOS circuit having a p.sup.- -substrate in which the n.sup.+ -source and drain regions of an N-channel MOS transistor are formed, and an n.sup.- -well region in which the p.sup.+ -drain and source regions of a P-channel MOS transistor and an n.sup.+ -type well contacting region are located. Such a semiconductor structure is shown in fragmentary and schematic manner in FIGS. 1 to 3. In these figures, the well region is designated W, the well contacting region is designated WK, the drain regions are designated D and the source regions are designated S. The semiconductor junctions between drain and source regions constitute, together with the material in which they are embedded, semiconductor diodes which may be blocking or conducting, depending on the bias voltage present across these semiconductor junctions. In FIGS. 1 to 3, such diodes, which hereinafter are referred to as parasitic diodes, are shown in broken lines for the P-channel MOS transistor located in well region W. The drain well diode thereof is designated DWVD, and the source well diode SWD.
There are circuit arrangements, for example driver circuits for liquid crystal display devices (LCD) to which is supplied on the one hand a positive supply voltage potential VDD of a supply voltage source and on the other hand a positive LCD operating voltage VLCD. While the supply voltage potential VDD generally has a constant potential value, the LCD operating voltage VLCD is mostly variable, for example for being able to adjust a desired contrast or for temperature tracking, through which the effects of temperature fluctuations are compensated. The variability of VLCD in relation to VDD may have the result that VLCD at one moment of time is greater than VDD and at a different moment of time is smaller than VDD.
In practical application, the two possibilities shown in FIGS. 2 and 3 exist, namely to apply VDD to the source region S of the P-channel MOS transistor located in well region W and to apply VLCD to the well contacting region WK FIG. 2), or vice versa to apply VLCD to the source region of this P-channel MOS transistor and VDD to the well contacting region WK (FIG. 3).
The two parasitic diodes DWD and SWD normally should be blocked in order to avoid transverse and leakage currents that may lead to falsification of the electrical behavior of the integrated semiconductor circuit, possibly to such an extent that this semiconductor circuit no longer fulfills the prescribed specification.
For keeping the parasitic diode SWD in the blocked state or off-state, the condition VDD.ltoreq.VLCD must be fulfilled in case of FIG. 2, whereas in case of FIG. 3 the condition VLCD.ltoreq.VDD must be fulfilled. This means that none of the two alternatives depicted in FIGS. 2 and 3 permits that the values of the two potentials VDD and VLCD are made independent of each other.
FIG. 4 shows an example of voltage patterns of VDD and VLCD. It is assumed in this respect that VLCD, when the value thereof is to be variable in the manner desired, is between a minimum value VLCDmin and a maximum value VLCDmax, whereas VDD has a constant potential between these values. However, this desired alteration range of VLCD can be realized neither in case of FIG. 2 nor in case of FIG. 3, when it is to be ensured that the parasitic diode SWD remains blocked. In case of FIG. 2, only the range between VDD and VLCDmax can be utilized for VLCD, whereas in case of FIG. 3 only the range between VLCDmin and VDD can be utilized for VLCD.
Corresponding considerations can be made for a semiconductor circuit in which substrate or epitaxial layer, well region W, well contacting region WK, drain region D and source region S are of conductivity types that are opposite to the conductivity types shown in FIGS. 1 to 3. Such a semiconductor circuit usually is operated with negative supply or operating voltages which, just as with the examples elucidated by way of FIGS. 2 and 3, cannot be independent of each other when it is to be ensured that the parasitic diode SWD remains blocked.
As regards parasitic diodes DWD, similar considerations are applicable as for parasitic diodes SWD. Due to the fact that the amount of the potential VD present at drain region D, because of the voltage drop across the channel distance, usually is lower than the value of the potential present at the source region, when the parasitic diode DWD remains blocked, then such conditions are observed for VDD and VLCD that parasitic diode SWD remains blocked too.
It is known from U.S. Pat. No. 5,444,397 with respect to a semiconductor structure in which a P-channel MOS transistor is formed in a well region and one of two different potentials of the same sign may be applied in alternative manner to the drain region, with said potentials having different values, to apply to the well contacting region a potential having the same sign as the two potentials that may be applied to the drain region in alternative manner, and having a value that is as large as the maximum value which may be assumed by the two potentials that may be alternatively applied to the drain region.
In case of the example elucidated by way of FIGS. 2 and 3, in which a supply voltage potential VDD or an LCD operating potential VLCD, with voltage values and ranges according to FIG. 4, can be applied in alternative manner to the source region of a P-channel MOS transistor located in a well region, the application of the teaching according to U.S. Pat. No. 5,444,397 has the result that a potential is applied to the well contacting region which on the one hand is positive and the potential value of which on the other hand is equal to or greater than VDD or VLCDmax, depending on whether the value of VDD or the value of VLCDmax is greater.
The two potentials which alternatively are applicable, for example, to the source region of a MOS transistor formed in a well region, may be selected in completely independent manner with respect to each other and may be made variable relative to each other as desired, without causing an undesired conduction of the parasitic diodes. Care merely has to be taken that the potential applied to the well contacting region has a value which is equal to or greater than the value that may be assumed at maximum by the two potentials alternatively applicable to the source region.